A Mask Read Only Memory (Mask ROM) is a semiconductor memory device in which data required is coded during a manufacturing process. There are, generally, two types of Mask ROMs: an embedded diffusion-programmable ROM and an embedded metal programmable ROM. Whether a mask ROM is an embedded diffusion-programmable ROM or an embedded metal programmable ROM, depends on the manufacturing process. Specifically, in the case of the embedded diffusion programmable ROM, its ROM data is programmed during a diffusion process, whereas in the case of the embedded metal programmable ROM, its ROM data is programmed during a metal/metallization process. Additionally, in an embedded via programmable ROM, which is similar to the embedded metal programmable ROM, its ROM data code is programmed during a via process.
Generally, the embedded diffusion-programmable ROM has been preferred to the embedded metal programmable ROM, mainly because the integration density of the former is typically higher than that of the latter by about from 25% to 35%.
However, compared to the embedded metal programmable ROM, it typically takes more time to manufacture the embedded diffusion-programmable ROM after data is received from a user. Recently, increased interest has been shown in the embedded metal (or via) programmable ROM, not only because the integration density thereof has been largely improved as techniques of manufacturing semiconductors have developed, but also because it is advantageous in terms of “Time-to-Market.”
FIG. 1 illustrates a two-column bit memory cell structure of a conventional embedded metal programmable ROM. Referring to FIG. 1, a conventional metal programmable ROM includes first and second word lines WL1 and WL2, first and second bit lines BL1 and BL2, a virtual grounding line VGND and first through fourth NMOS cell transistors n11–n14.
A first side of each of the first through fourth NMOS cell transistors n11–n14 is connected to the virtual grounding line VGND. Also, the gates of the first and third cell transistors n11 and n13 and the gates of the second and fourth cell transistors n12 and n14 are connected to the first word line WL1 and the second word line WL2, respectively.
Referring to FIG. 1, data 0, 1 and data 0, 0 are coded in two bit cells selected by the first word line WL1 and two bit cells selected by the second word line WL2, respectively. When the data 0, 1 is coded in two bit cells selected by the first word line WL1 the second side of the first cell transistor n11 is connected to the first bit line BL1 and the second side of the first cell transistor n13 is floated. On the other hand, when the data 0, 0 is coded in two bit cells selected by the second word line WL2, the second sides of the second cell transistor n12 and the fourth cell transistor n14 are connected to the first bit line BL1 and the second bit line BL2, respectively.
FIG. 2 shows a four-column bit memory structure of a conventional metal programmable ROM. Referring to FIG. 2, the four-column bit memory cell of a conventional metal programmable ROM includes first and second word lines WL1 and WL2, first and second bit lines BL1 and BL2, first to third virtual grounding lines VGND1–VGND3 and first through eighth NMOS cell transistors n21–n28.
A first side of each of the first and second cell transistors n21–n22 is connected to the first virtual grounding line VGND1. A first side of each of the third through sixth NMOS cell transistors n23–n26 and a first side of each of the seventh and eighth cell transistors n27 and n28 are connected to the second virtual grounding line VGND2 and the third virtual grounding line VGND3, respectively.
Further, the first word line WL1 is connected to the gates of the first, third, fifth and seventh cell transistors n21, n23, n25 and n27 and the second word line WL2 is connected to the gates of the second, fourth, sixth and eight cell transistors n22, n24, n26 and n28.
FIG. 2 shows that data 0, 0, 1, 0 and 1, 0, 1, 1 are coded in four bit cells selected by the first word line WL1 and four bit cells selected by the second word line WL2. If data 0, 0, 1, 0 are coded in four bit cells selected by the first word line WL1, the second sides of the first and third cell transistors n21 and n23 are connected to the first bit line BL1, the second side of the fifth cell transistor n25 is floated and the second side of the seventh cell transistor n27 is connected to the second bit line BL2. On the other hand, when data 1, 0, 1, 1 are coded in four bit cells selected by the second word line WL2, the second sides of the second, sixth and eighth cell transistors n22, n26 and n28 are floated and the second side of the fourth cell transistor n24 is connected to the first bit line BL1.
The above-described conventional metal programmable ROMs, however, may have a disadvantage in that the size thereof may be larger than that of a conventional embedded diffusion programmable ROM because diffusion domains that hold a bit line in common are separated from one another. Furthermore, the reading speed may be increased over that of a conventional embedded diffusion programmable ROM due to an increase in the loaded capacitance of a bit line which may also result in an increase in power consumption.